The present invention relates to a method for fabricating a semiconductor device and, more particularly, to a method for forming fine patterns in a semiconductor device.
Generally, with the increase in integration of a semiconductor device, the miniaturization of patterns is essentially required; however, there is a limit to the pattern miniaturization in the semiconductor device because current photolithography apparatus is also limited to a restricted light wavelength.
In order to solve the above-mentioned problem, a double patterning process which forms the fine patterns using two sheets of the photo masks has been proposed recently. The double patterning process makes it possible to form the fine patterns beyond the limit to the photolithography apparatus. Referring to FIG. 1A to 1D, the double patterning process will be described below.
FIGS. 1A to 1D are cross-sectional views of a method for forming fine patterns in a typical semiconductor device.
Referring to FIG. 1A, after a hard mask layer 11 is formed over an etch target layer 10, the hard mask layer 11 is coated with a first photoresist layer. The first photoresist layer is patterned by exposing and developing processes and then photoresist patterns 12 are formed. The photoresist patterns 12 have a space width S1. Next, the hard mask layer 11 is etched using the first photoresist patterns 12 as an etch mask.
Referring to FIG. 1B, after removing the first photoresist patterns 12, a second photoresist layer is deposited on the resultant structure and exposing and developing processes are applied to the second photoresist layer to form the second photoresist patterns 13. The second photoresist patterns 13 have a space width S2. The openings of the second photoresist patterns 13 are formed in such a manner that they do not overlap with the openings of the first photoresist patterns 12.
Referring to FIG. 1C, the hard mask layer 11 is etched using the second photoresist patterns 13 as an etch mask, thereby forming hard mask patterns 11′. Since the hard mask patterns 11′ are formed by two etching processes, the line and space widths of the hard mask patterns 11′ are reduced.
Referring to FIG. 1D, the etch target layer 10 is etched using the hard mask patterns 11′ as an etch mask so that etch target patterns 10′ are formed. At this time, the etch target patterns 10′ have the line and space widths which are correspondent to the line and space widths of the hard mask patterns 11′.
However, even if this double patterning process is applied to the pattern formation, it is still difficult to form the micro patterns of less than 20 nm. The reason for the difficulties of the pattern formation is as follows.
In the pattern formation using the double patterning process, the most importance is to reduce the space widths (S1 and S2 in FIGS. 1A and 1B) between the first and the second photoresist patterns which are used as the etch masks. However, it is difficult to form the space widths of less than 20 nm because of the limit of the current photolithography apparatus. If the space widths between the photoresist patterns are formed in a range of below 20 nm, the failure to the device may be caused by the bridges and bad patterns. Therefore, it is very difficult to form the fine patterns of less than 20 nm through the photoresist patterns which have the space widths of less than 20 nm.
Further, in case a lower layer is etched using a general photoresist pattern, the wider the space widths formed in the lower layer is, the higher the aspect ratio of the lower layer is. Therefore, it is difficult to form the micro patterns in case the aspect ratio of the lower layer (the hard mask layer and/or the etch target layer) under the photoresist pattern is higher.
Accordingly, the technology capable of forming the fine patterns is needed in a state where the space widths of the photoresist patterns are wide and the aspect ratio of the lower layer is high.